iskalni niz: ternary logic
iskanje: IEEE Explore
pomembni: 67, 

5. Yamamoto, Y.; Mukaidono, M., Meaningful special classes of ternary logic functions-regular ternary logic functions and ternary majority functions, IEEE Transactions on Computers, Volume 37,  Issue 7,  July 1988 Page(s):799 - 806, DOI: 10.1109/12.2225  

7. Rajashekhara, T.N.; Chen, I.-S.E., A fast adder design using signed-digit numbers and ternary logic, Southern Tier Technical Conference, 1990., Proceedings of the 1990 IEEE 25 April 1990 Page(s):187 - 194, 
DOI: 10.1109/STIER.1990.324644 

11. Takagi, N.; Nakashima, K., Some properties of discrete interval truth valued logic, Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on 23-25 May 2000 Page(s):101 - 106, 
DOI: 10.1109/ISMVL.2000.848606

14. Huang, Z.; Rine, D.C., B-ternary logic and evaluation of binary logic programs, Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on 24-26 May 1988 Page(s):376 - 380 ,
DOI: 10.1109/ISMVL.1988.5198 


17. Jialin Wu; Ternary logic circuit for error detection and error correction, Multiple-Valued Logic, 1989. Proceedings., Nineteenth International Symposium on 29-31 May 1989 Page(s):94 - 99, DOI: 10.1109/ISMVL.1989.37766 

18. Takagi, N.; Nakashima, K.; Discrete interval truth values logic and its application, IEEE Transactions on Computers, Volume 49,  Issue 3,  March 2000 Page(s):219 - 229, DOI: 10.1109/12.841126 

23. Hata, Y.; Nakashima, K.; Yamato, K.; Some fundamental properties of multiple-valued Kleenean functions and determination of their logic formulas, IEEE Transactions on Computers, Volume 42, Issue 8, Aug. 1993 
Page(s):950 - 961, DOI: 10.1109/12.238485 


25. Wu, X.W.; Prosser, F.P.; CMOS ternary logic circuits, Circuits, Devices and Systems, IEE Proceedings G
Volume 137,  Issue 1,  Feb. 1990 Page(s):21 - 27

35. Benchu Fei; Qinghua Hong; Gongli Zhang; Identification of linear ternary logic functions and its algorithms,
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on 25-27 May 1994 Page(s):324-327, 
DOI: 10.1109/ISMVL.1994.302183

39. Nagaraj, K.; Ramkumar, K.; Static RAM cell for ternary logic, Proceedings of the IEEE
Volume 72,  Issue 2,  Feb. 1984 Page(s):227 - 228

54. Morisue, M.; Endo, J.; Morooka, T.; Shimizu, N.; Sakamoto, M.; A Josephson ternary memory circuit,
Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on
27-29 May 1998 Page(s):19 - 24, DOI: 10.1109/ISMVL.1998.679270 

58. Hata, Y.; Nakashima, K.; Yamato, K.; Some relationships between multiple-valued Kleenean functions and ternary input multiple-valued output functions, Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on 23-25 May 1990 Page(s):410 - 417, DOI: 10.1109/ISMVL.1990.122656

67. Serran, N.V.; Jorge, A.M.; Dias, J.A.S.; A proposal for the implementation of ternary digital circuits,
Microelectronics, 1995. Proceedings., 1995 20th International Conference on Volume 2,  12-14 Sept. 1995 
Page(s):485 - 490 vol.2, DOI: 10.1109/ICMEL.1995.500914 

75. Fu-Qiang Li; Morisue, M.; Ogata, T.; A proposal of Josephson binary-to-ternary converter,
Applied Superconductivity, IEEE Transactions on Volume 5,  Issue 2,  Part 3,  Jun 1995 Page(s):2632 - 2635,
DOI: 10.1109/77.403130

88. Choi, L.-J.; Bailey, J.M.; Design and implementation of ternary exoatmospheric autopilot system,
Digital Avionics Systems Conference, 1990. Proceedings., IEEE/AIAA/NASA 9th 15-18 Oct. 1990 Page(s):58 - 63 
DOI: 10.1109/DASC.1990.111262

89. Hong-Yi Huang; Chung-Yu Wu; Redundant algebra and integrated circuit implementation of ternary logic and their applications, Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
3-6 May 1993 Page(s):1905 - 1908

93. Itazaki, N.; Kinoshita, K.; Test pattern generation for circuits with tri-state modules by Z-algorithm,
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 8,  Issue 12,  Dec. 1989 Page(s):1327 - 1334, DOI: 10.1109/43.44513



iskalni niz: three valued logic
iskanje: IEEE Explore
pomembni:


35. Bahraini, M.; Epstein, G.; Three-valued Karnaugh maps, Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on 24-26 May 1988 Page(s):178 - 185 , DOI: 10.1109/ISMVL.1988.5171



iskalni niz: multi valued logic
iskanje: IEEE Explore
pomembni:

6. Drechsler, R.; Keim, M.; Becker, B.; Fault simulation in sequential multi-valued logic networks,
Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on 28-30 May 1997 Page(s):145 - 150,
DOI: 10.1109/ISMVL.1997.601389

41. Lewis, T.; Perkowski, M.; Jozwiak, L.; Learning in hardware: architecture and implementation of an FPGA-based rough set machine, EUROMICRO Conference, 1999. Proceedings. 25th Volume 1,  8-10 Sept. 1999 Page(s):326-334 vol.1,
DOI: 10.1109/EURMIC.1999.794488